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PRELIMINARY
W48C111-16
Frequency Generator for Integrated Core Logic
Features
* Maximized EMI suppression using Cypress's Spread Spectrum technology * Power-on default to spread mode * Two copies of CPU output * Six copies of PCI output (synchronous w/CPU outputs) * One copy of 48-MHz USB output * One Buffered copy of 14.318-MHz input reference signal * Supports 100-MHz or 66-MHz CPU operation * Power management control input pins * Low Frequency Test Mode * Available in 28-pin SSOP (209 mil) CPU0:1 Skew: ............................................................ 175 ps CPU0:1 Cycle to Cycle Jitter: ..................................... 200 ps PCI_F, PCI1:5 Skew: ...................................................500 ps PCI_F, PCI1:5 Cycle to Cycle Jitter: ............................ 250 ps CPU to PCI Skew: ........................ 1.5 to 4.0 ns (CPU Leads) Output Duty Cycle: .................................................... 45/55% PCI_F, PCI Edge Rate: .............................................. >1 V/ns CPU_STOP#, PWR_DWN#, PCI_STOP#: 250-k pull-up resistor Table 1. Pin Selectable Frequency SEL100/66# 0 1 CPU(0:1) 66.6 MHz 100 MHz PCI 33.3 33.3 Spread% 0.5% 0.5%
Key Specifications
Supply Voltages: ....................................... VDDQ3 = 3.3V5% VDDQ2 = 2.5V5%
Block Diagram
VDDQ3 REF X1 X2 XTAL OSC PLL Ref Freq
Pin Configuration
X1 X2 GND PCI_F PCI1 VDDQ3
VDDQ2
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
GND VDDQ3 REF VDDQ2 CPU0 CPU1 GND VDDQ3 GND PCI_STOP# CPU_STOP# PWR_DWN# 48MHz SEL100/66#
PCI2 PCI3 VDDQ3 PCI4 PCI5 GND VDDQ3
CPU_STOP# Stop Clock Control SEL100/66# PLL 1 /2//3
CPU0 CPU1
VDDQ3 PCI_F Stop Clock Control PCI_STOP# VDDQ3 PCI4 PCI5 PWR_DWN# Power Down Control VDDQ3 PLL 2 48MHz PCI1 PCI2 PCI3
GND
Cypress Semiconductor Corporation
*
3901 North First Street
*
San Jose
*
CA 95134 * 408-943-2600 November 2, 1999, rev. **
PRELIMINARY
Pin Definitions
Pin Name CPU0:1 Pin No. 24, 23 Pin Type O Pin Description
W48C111-16
CPU Clock Outputs 0 and 1: These two CPU clock outputs are controlled by the CPU_STOP# control pin. Output voltage swing is controlled by voltage applied to VDDQ2. PCI Bus Clock Outputs 1 through 5: These five PCI clock outputs are controlled by the PCI_STOP# control pin. Output voltage swing is controlled by voltage applied to VDDQ3. Fixed PCI Clock Output: Unlike PCI1:5 outputs, this output is not controlled by the PCI_STOP# control pin; it cannot be forced LOW by PCI_STOP#. Output voltage swing is controlled by voltage applied to VDDQ3. 48-MHz Output: Fixed clock output at 48 MHz. Output voltage swing is controlled by voltage applied to VDDQ3. This output does not have the SS feature CPU_STOP# input: When brought LOW, clock outputs CPU0:1 are stopped LOW after completing a full clock cycle (2-3 CPU clock latency). When brought HIGH, clock outputs CPU0:1 start with a full clock cycle (2-3 CPU clock latency). PCI_STOP# input: The PCI_STOP# input enables the PCI1:5 outputs when HIGH and causes them to remain at logic 0 when LOW. The PCI_STOP signal is latched on the rising edge of PCI_F. Its effect takes place on the next PCI_F clock cycle. Fixed 14.318-MHz Output: Used for various system applications. Output voltage swing is controlled by voltage applied to VDDQ3. Frequency Selection Inputs: Select power-up default CPU clock frequency as shown in Table 1 on page 1. Crystal Connection or External Reference Frequency Input: This pin can either be used as a connection to a crystal or to a reference signal. Crystal Connection: An input connection for an external 14.318-MHz crystal. If using an external reference, this pin must be left unconnected. Power-Down Control: When this input is LOW, device goes into a low-power standby condition. All outputs are held LOW. CPU and PCI clock outputs are stopped LOW after completing a full clock cycle (2-3 CPU clock cycle latency). When brought HIGH, CPU and PCI outputs start with a full clock cycle at full operating frequency (3 ms maximum latency). Power Connection: Connected to 3.3V supply. Power Connection: Power supply for CPU0:1 output buffer. Connected to 2.5V or 3.3V. Ground Connection: Connect all ground pins to the common system ground plane.
PCI1:5
5, 7, 8, 10, 11 4
O
PCI_F
O
48MHz CPU_STOP#
16 18
O I
PCI_STOP#
19
I
REF SEL100/66# X1 X2 PWR_DWN#
26 15 1 2 17
O I I I I
VDDQ3 VDDQ2 GND
6, 9, 13, 21, 27 25 3, 12, 14, 20, 22, 28
P P G
2
PRELIMINARY
Spread Spectrum Feature
The device generates a clock that is frequency modulated in order to increase the bandwidth that it occupies. By increasing the bandwidth of the fundamental and its harmonics, the amplitudes of the radiated electromagnetic emissions are reduced. This effect is depicted in Figure 1. As shown in Figure 1, a harmonic of a modulated clock has a much lower amplitude than that of an unmodulated signal. The reduction in amplitude is dependent on the harmonic number and the frequency deviation or spread. The equation for the reduction is: dB = 6.5 + 9*log10(P) + 9*log10(F)
5dB /div
W48C111-16
Where P is the percentage of deviation and F is the frequency in MHz where the reduction is measured. The output clock is modulated with a waveform depicted in Figure 2. This waveform, as discussed in "Spread Spectrum Clock Generation for the Reduction of Radiated Emissions" by Bush, Fessler, and Hardin produces the maximum reduction in the amplitude of radiated electromagnetic emissions. The deviation selected for this chip is 0.5% of the center frequency. Figure 2 details the Cypress spreading pattern. Cypress does offer options with more spread and greater EMI reduction. Contact your local Sales representative for details on these devices. Spread Spectrum clocking is always active on this device.
S SFT G
Typ ical C lock
Amplitude (dB)
-SS %
F requ en cy Sp an (M Hz)
+S S%
Figure 1. Clock Harmonic with and without SSCG Modulation Frequency Domain Representation
MAX (+0.5%)
FREQUENCY
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
10%
20%
30%
40%
50%
60%
70%
80%
90%
MIN (-0.5%)
Figure 2. Typical Modulation Profile
3
100%
PRELIMINARY
Absolute Maximum Ratings
Stresses greater than those listed in this table may cause permanent damage to the device. These represent a stress rating only. Operation of the device at these or any other conditions Parameter VDD, VIN TSTG TA TB ESDPROT Description Voltage on any pin with respect to GND Storage Temperature Operating Temperature Ambient Temperature under Bias Input ESD Protection
W48C111-16
above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability. Rating -0.5 to +7.0 -65 to +150 0 to +70 -55 to +125 2 (min.) Unit V C C C kV
DC Electrical Characteristics: TA = 0C to +70C, VDDQ3 = 3.3V5%, VDDQ2 = 2.5V5%, CPU0:1 = 66.6/100 MHz
Parameter Supply Current IDD3 IDD2 VIL VIH IIL IIH IIL IIH VOL VOH VOH IOL Combined 3.3V Supply Current 2.5V Supply Current Input Low Voltage Input High Voltage Input Low Current[2] Input High Current[2] Input Low Current (SEL100/66#) Input High Current (SEL100/66#) Output Low Voltage Output High Voltage Output High Voltage Output Low Current CPU0:1 CPU0:1 PCI_F, PCI1:5 REF IOH Output High Current CPU0:1 PCI_F, PCI1:5 REFX Crystal Oscillator VTH CLOAD CIN,X1 CIN COUT LIN X1 Input Threshold Voltage[3] Load Capacitance, as seen by External Crystal[4] X1 Input Capacitance[5] Input Pin Capacitance Output Pin Capacitance Input Pin Inductance Pin X2 unconnected Except X1 and X2 VDDQ3 = 3.3V 1.65 14 28 5 6 7 V pF pF pF pF nH IOL = 1 mA IOH = -1 mA IOH = -1 mA VOL = 1.25V VOL = 1.5V VOL = 1.5V VOL = 1.25V VOL = 1.5V VOL = 1.5V 3.1 2.2 55 20.5 25 50 31 27 115 53 37 110 55 44 190 139 76 195 189 94 GND - 0.3 2.0 Outputs Loaded[1] 80 40 0.8 VDD + 0.3 -25 10 -5 5 50 mA mA V V A A A A mV V V mA mA mA mA mA mA Description Test Condition Min. Typ. Max. Unit
Logic Inputs
Clock Outputs
Pin Capacitance/Inductance
Notes: 1. All clock outputs loaded with 6" 60 transmission lines with 20-pF capacitors. 2. CPU_STOP#, PCI_STOP#, and PWRDWN# logic inputs have internal pull-up resistors (pull-ups not CMOS level). 3. X1 input threshold voltage (typical) is VDDQ3/2. 4. The W48C111-16 contains an internal crystal load capacitor between pin X1 and ground and another between pin X2 and ground. Total load placed on crystal is 14 pF; this includes typical stray capacitance of short PCB traces to crystal. 5. X1 input capacitance is applicable when driving X1 with an external clock source (X2 is left unconnected).
4
PRELIMINARY
AC Electrical Characteristics
TA = 0C to +70C, VDDQ3 = 3.3V5%,VDDQ2 = 2.5V 5%, fXTL = 14.31818 MHz
W48C111-16
AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the clock output. CPU Clock Outputs, CPU0:1 (Lump Capacitance Test Load = 20 pF) CPU = 66.6 MHz Parameter tP tH tL tR tF tD tJC Description Period High Time Low Time Output Rise Time Output Fall Time Duty Cycle Jitter, Cycle-to-Cycle Test Condition/Comments Measured on rising edge at 1.25V Duration of clock cycle above 2.0V Duration of clock cycle below 0.4V Measured from 0.4V to 2.0V Measured from 2.0V to 0.4V Measured on rising and falling edge at 1.25V Measured on rising edge at 1.25V. Maximum difference of cycle time between two adjacent cycles. Measured on rising edge at 1.25V Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Average value during switching transition. Used for determining series termination value. 13.5 15 5.2 5.0 0.4 0.4 45 1.6 1.6 55 200 15.5 CPU = 100 MHz Typ. Max. Unit 10.5 ns ns ns 1.6 1.6 55 250 V/ns V/ns % ps 10 3.0 2.8 0.4 0.4 45 Min. Typ. Max. Min.
tSK fST
Output Skew Frequency Stabilization from Power-up (cold start) AC Output Impedance
175 3
175 3
ps ms
Zo
13.5
PCI Clock Outputs, PCI1:5 and PCI_F (Lump Capacitance Test Load = 30 pF CPU = 66.6/100 MHz Parameter tP tH tL tR tF tD tJC tSK tO fST Description Period High Time Low Time Output Rise Edge Rate Output Fall Edge Rate Duty Cycle Jitter, Cycle-to-Cycle Output Skew CPU to PCI Clock Skew Frequency Stabilization from Power-up (cold start) AC Output Impedance Test Condition/Comments Measured on rising edge at 1.5V Duration of clock cycle above 2.4V Duration of clock cycle below 0.4V Measured from 0.4V to 2.4V Measured from 2.4V to 0.4V Measured on rising and falling edge at 1.5V Measured on rising edge at 1.5V. Maximum difference of cycle time between two adjacent cycles. Measured on rising edge at 1.5V Covers all CPU/PCI outputs. Measured on rising edge at 1.5V. CPU leads PCI output. Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Average value during switching transition. Used for determining series termination value. 30 1.5 Min. 30 12 12 1 1 45 4 4 55 250 500 4 3 Typ. Max. Unit ns ns ns V/ns V/ns % ps ps ns ms
Zo
5
PRELIMINARY
REF Clock Output (Lump Capacitance Test Load = 20 pF)
W48C111-16
CPU = 66.6/100 MHz Parameter f tR tF tD tJC fST Description Frequency, Actual Output Rise Edge Rate Output Fall Edge Rate Duty Cycle Jitter, Cycle to Cycle Frequency Stabilization from Power-up (cold start) AC Output Impedance Test Condition/Comments Frequency generated by crystal oscillator Measured from 0.4V to 2.4V Measured from 2.4V to 0.4V Measured on rising and falling edge at 1.5V Measured on rising edge at 1.5V. Maximum difference of cycle time between two adjacent cycles. Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Average value during switching transition. Used for determining series termination value. 40 1 1 45 Min. Typ. 14.318 4 4 55 500 3 Max. Unit MHz V/ns V/ns % ps ms
Zo
48-MHz Clock Output (Lump Capacitance Test Load = 20 pF) CPU = 66.6/100 MHz Parameter f fD m/n tR tF tD tJC Description Frequency, Actual Deviation from 48 MHz PLL Ratio Output Rise Edge Rate Output Fall Edge Rate Duty Cycle Jitter, Cycle to Cycle Test Condition/Comments Determined by PLL divider ratio (see m/n below) (48.008 - 48)/48 (14.31818 MHz x 57/17 = 48.008 MHz) Measured from 0.4V to 2.4V Measured from 2.4V to 0.4V Measured on rising and falling edge at 1.5V Measured on rising edge at 1.5V. Maximum difference of cycle time between two adjacent cycles. Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Average value during switching transition. Used for determining series termination value. 40 0.5 0.5 45 Min. Typ. 48.008 +167 57/17 2 2 55 500 V/ns V/ns % ps Max. Unit MHz ppm
fST
Frequency Stabilization from Power-up (cold start) AC Output Impedance
3
ms
Zo
Ordering Information
Ordering Code W48C111 Document #: 38-00844 Freq. Mask Code -16 Package Name H Package Type 28-pin SSOP (209 mils)
6
PRELIMINARY
Package Diagram
28-Pin Small Shrink Outline Package (SSOP, 209 mils)
W48C111-16
(c) Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

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